Advanced silicon bipolar, CMOS or BiCMOS circuits are used today for high-speed applications in the 1–5 GHz frequency range, replacing circuits previously only possible to realize using III–V based technologies.
A common trend in microelectronics is to integrate more and more functions on a single chip, in order to increase the general performance and to reduce size, power consumption and price of the circuits. The versatility of a BiCMOS process is many time preferred, although it is not suited for all applications. High-performance bipolar integrated circuits have been used extensively for some critical building blocks in telecommunication circuits, mainly for analog functions such as switching currents and voltages, and for high-frequency radio circuit functions such as those in mixers, amplifiers, and detectors. For high-performance cost-effective circuits that would be used in e.g. cellular telephones, a bipolar-only process is many times still to prefer, instead of a BiCMOS process.
All modern high-frequency bipolar transistors apply polysilicon emitter technology. The emitter is formed by depositing a polysilicon layer, which is then heavily doped. When activated, preferably using RTA (rapid thermal anneal), the dopants are driven into the underlying substrate. A very thin emitter depth, which also permits thin bases (translates into good high frequency properties) is achieved. Another feature of polysilicon emitter technology is the increased beta, which is strongly related to the details of the interface between the polysilicon layer and the substrate.
Although in most RF-IC design the n-type devices, i.e. NPN transistors, are totally dominating, p-type devices, i.e. PNP-transistors, are needed for some circuit functions. However, a bipolar-only RF-IC process usually lacks good PNP-transistors, since the process is commonly designed for optimal vertical NPN transistor performance. High-performance vertical PNP-transistors can be added to the process flow, but to a cost of increased processing complexity and number of mask layers, see e.g. M. C. Wilson et al., “Process HJ: A 30 GHz NPN and 20 GHz PNP Complimentary Bipolar Process for High Linearity RF Circuits”, Proc. IEEE BCTM Conf. 1998, p. 164.
Instead, lateral PNP transistors are usually employed as p-type devices, since the requirement can be very relaxed in terms of high-frequency properties, current drive ability, packing density etc.
The lateral PNP transistor is commonly made by placing two p-type diffusions in close proximity to each other in the epi-layer, one of them, the collector, surrounding the other one, the emitter. In most RF-IC processes, the base will consist of the n-well, with the subcollector used as base contact. The collector and emitter regions are separated by field oxide. A typical example of a lateral PNP device in a BiCMOS process is described in U.S. Pat. No. 5,953,600 by Gris.
The basic function of a MOS-gated lateral PNP-transistor is described in EP 0 093 086 by Vittoz, which points out that the gate should be biased so that the inversion in the MOS channel regions is avoided, i.e. the MOS transistor should always be off. U.S. Pat. No. 5,326,710 by Joyce et al. further describes integration of a lateral PNP device in a BiCMOS process using not only a plain MOS transistor, but also an additional nitride in the gate dielectric. EP 0 872 893 by Laurens describes an optimized lateral PNP transistor using MOS devices in a BiCMOS process.
A lateral PNP transistor by using MOS transistors is usually layouted in a circular manner. In the center of the layout is the emitter (source), surrounded by the gate. The MOS gate is connected to the emitter (source), to assure that the channel of the MOS device is always in accumulation.
A primary problem with the lateral PNP devices made by using MOS transistors is the low gain (beta), which typically is lower than 10. Another problem is the comparatively large area occupied by each device. An optimized structure is therefore needed.